ECEPC-312 Digital System Design
Teaching Scheme			Credit	Marks Distribution			Duration of End Semester Examination
L	T	P		Internal Assessment	End Semester Examination	Total
3	0	0	3	Maximum Marks: 40	Maximum Marks: 60	100	3 Hours
				Minimum Marks: 16	Minimum Marks: 24	40

Unit-I

Number system and codes: Review of Boolean Algebra, Binary arithmetic (Addition, Subtraction, Multiplication and Division), Floating point numbers. BCD codes, 8421 code, Excess-3 code, Gray code, Error detection and correction: Parity code, Hamming code.

Logical Simplification: De Morgan's Theorem, SOP & POS forms, Canonical forms, Karnaugh maps up to 6 variables. The tabulation method, Determination of prime implicants, Selection of essential prime implicants. Quine Mccluskey method.

Unit-II

Combinational Logic Design: MSI devices like Comparators, Multiplexers, Encoder, Decoder, Driver & Multiplexed Display, Half and Full Adders, Subtractors, Serial and Parallel Adders, BCD Adder, Barrel shifter and ALU.

Logic families: TTL NAND gate, Specifications, Noise margin, Propagation delay, fan-in, fan-out, Tristate TTL, ECL, CMOS families and their interfacing, Memory elements, Concept of programmable logic devices like FPGA, Logic implementation using programmable Devices.

Unit-III

Sequential Logic Design: Building blocks like S-R, JK and Master-Slave JK FF, Edge triggered FF, Ripple and Synchronous counters, Shift registers, Finite state machines, Design of synchronous FSM, Algorithmic State Machines charts. Designing synchronous circuits like Pulse train generator, Pseudo Random Binary Sequence generator, Clock generation.

Unit-IV

VLSI Design flow: Design entry: Schematic, FSM & HDL, different modelling styles in VHDL, Data types and objects, Dataflow, Behavioural and Structural Modelling, Synthesis and Simulation VHDL constructs and codes for combinational and sequential circuits.